IMPLEMENTATION OF LOW-POWER DIGITAL CONTROLLED OSCILLATOR
Keywords:
clock signal oscillator, power consumption, integrated circuit, simulationAbstract
A digital controlled oscillator design is proposed, working in sleep and generation modesÿ providing an output clock signal in the frequency range from 1.6GHz to 2.5GHz. The designed system shows less power consumption compared to the existing solutions, at the same time, maintaining sufficient stability of the output signal at supply voltage variations.
