INTRODUCTION OF A CUSTOMIZABLE RTL AND UVM TESTBENCH GENERATOR

Abstract

In the rapidly evolving landscape of hardware design, the need for more versatile, 
efficient, and user-friendly tools is ever-growing. Traditional hardware design workflows 
spanning from component selection to Register Transfer Level (RTL) coding, verification, 
and Field Programable Gate Array (FPGA) implementation are often time-consuming and 
require deep technical expertise. Introducing novel python command-line-based tool, a 
groundbreaking solution that empowers engineers to create customized hardware projects, 
configure essential modules such as memory, memory controllers, and Central Procesing 
Units (CPU), and then seamlessly and automatically generate RTL code, Universal 
Verification Methodologies (UVM) testbenches, and even FPGA flow up to bitstream all in 
one place. Tool designed to streamline the workflow, reduce errors, and give engineers the 
flexibility to explore new design possibilities. By integrating multiple stages into a single, 
user-friendly platform, significantly reduces the time and effort required to develop 
complex hardware systems. 
Additionally, the tool offers a unique opportunity for users to create and import 
their own libraries of modules using a Python-based framework. Once these libraries are 
imported into a project, new modules can be created connected with other modules, and 
seamlessly integrated. The tool then automatically generates the necessary RTL code UVM 
test environment and basic FPGA flow for these custom modules, streamlining the entire 
development process.