A LINEARITY IMPROVEMENT METHOD FOR A HIGH-SPEED RECEIVER

Abstract

The demand for faster and more reliable data transmission has driven the development of high-speed Serliazlier/Deserializer (SerDes) systems. These systems are used in a wide range of applications, including high-performance computers, telecommunication equipment, and data centers. However, the high speeds involved in these systems can also lead to bandwidth limitation during data transmission. To address this issue, a four-level pulse amplitude modulation (PAM4) is seriously considered, as it offers higher spectral efficiency, lower loss at the Nyquist frequency, and relaxed clock speeds compared to simple binary non-return-to-zero (NRZ) signaling. The implementation of PAM4 modulation has led to the development of various high-speed I/O standards. Considering these developments, the linearity of the system became one of the main limiting factors for its performance. Therefore, it is essential to develop methods which are aimed at addressing this limitation. A linearity improvement method of high-speed dual-mode analog receivers is presented. These receivers are characterized by their ability to operate at high frequencies and the ability to provide a high level of signal integrity, which is critical for achieving high data rates and low error rates in high-speed systems. Dual mode receivers work for both NRZ and PAM4 modulations. The key advantages of high-speed receivers such as providing a high level of signal integrity, the circuit topologies, operating modes, and performance characteristics are discussed. The usage of the proposed method improves RLM by 6% and 1dB compression point by 119 mV in typical corner resulting in a 7% area increase.