READ AND WRITE CYCLE SPEEDUP METHOD FOR PSEUDO TWO-PORT SRAM WITH A 6T BIT CELL
Keywords:
SRAM, performance, speed, decoder, word line, two-portAbstract
Two-port 6T SRAM with improved read/write path is presented. The conventional two-port SRAM (2P-SRAM) with an 8T bit cell deliver has the best speed performance, but on the other hand, in some cases, speed can be degraded. To overcome the speed issue and improve the area, a two-port 6T SRAM is proposed, which can speed up the write/read cycle time by 60% and reduce the area by 14%. The disadvantage of this method is the output delay increase.
