DESIGN OF HIGH-SPEED CLOCKED COMPARATOR FOR THE 14NM CMOS TECHNOLOGICAL PROCESS

Abstract

High-speed comparators allow to get maximum speed while taking up less space. It is proposed to design a clocked comparator for the 14-nm CMOS technological process, which will have an input sensitivity of 4 milli volt at a clock rate of 3 Gigahertz. During the research, one scheme was observed, parametric optimization was performed through the SPICE model, physical modeling was performed using Custom Compiler. Results were displayed and measured using WaveView.