THE POWER DISTRIBUTION METHOD IN VLSI

Abstract

Power distribution supplies the power and the ground voltages from pad pins to all circuits in a design. Shrinking device dimensions, faster switching frequency and increasing power consumption in nowadays technologies cause large switching currents to flow in the power and ground networks. Power-supply integrity verification is, therefore, an essential issue in high-performance designs. Due to the resistance of the interconnects constituting the network, there occurs a voltage drop across the network, commonly referred to as the IR drop. The IR drop is predominantly caused by the parasitic resistance of metal wires constituting the on-chip power distribution network.

As a solution the problems described below, a new power distribution method to decrease the IR drop effect in VLSI circuits is described.