THE DISCLOSURE CORRECTING METHOD FOR THE 6T STATIC RANDOM-ACCESS MEMORY CELL

Abstract

The growth of devices with portable battery-operation has made low power IC design a priority in recent years. From this point of view, the design of low power and reliably embedded static random-access memory (SRAM) cells, which are a part of the modern System on the Chip (SoC) designs, have become one of the main areas of research. 

Significant increase of data transfer rates in conventional SRAM cells results in the reduction of circuit reliability because of the lack of required power and significant performance degradation in the era of fast mobile computing. The existing solutions do not meet modern requirements and can’t ensure functional operation. New approaches and solutions are needed for 6T Static random-access memory cells.

In the paper, a method for correcting the 6T static random-access memory is presented. The essence of the proposed method is the content of two different word lines, with the data transfer including two phases for each reading and writing operation. Also, the internal part of the cell is coupled with different supply voltages (they can be equal), which helps to avoid reading the issue and writing the failure during operations. This method allows to have more reliable data transfer and better performance. The comparison of SRAM with and without the correction method is done to prove the proposed method efficiency.