CONSIDERING THE DYNAMIC POWER OF LOGICAL ELEMENTS AT THEIR PLACING ON THE SUBSTRATE OF INTEGRATED CIRCUITS

Abstract

Technological scaling of integrated circuits (IC) significantly enhances the interconnection between the circuit design and physical parameters of IC. On the other hand, for modern highly integrated IC, the element placement is a fundamental step connecting all the other tasks of the integrated circuit physical design. The speed of IP, and reliability indicators associated with the thermal mode of its work largely depend on the element placement. With the constant growth of integration of IP and the increasing power density dispersion per unit area of the IC substrate, both the temperature of the semiconductor crystal and the thermal gradient on the substrate surface increase. The latter leads to the appearance of local topological heated zones, which become sources of a sharp decrease in the thermal reliability of the integrated circuit. In order to improve the thermal reliability of the IC, several methods of the element thermal distribution have been developed. These methods are aimed at equalizing the thermal field of the IC substrate, thereby helping to reduce the temperatures of the maximum heated local zones and increase the reliability. Since at the stage of IP element placement, the element base of the scheme is already known, in order to consider the thermal mode, it is necessary to estimate the power of the elements taking into account their work in the designed scheme.

In this paper, a method for estimating the real powers of the circuit logic elements is proposed, taking into account both the type of the element and the characteristics of the designed circuit and the place of this element in it. The proposed method is based on the evaluation of the switching element activities in a specific logical scheme and the application of these indicators when calculating their dynamic powers. In this case, it means that a specific library of digital logic elements serves as the element base. The paper also presents a method for considering the dynamic power of logic elements when they are placed on a substrate of integrated circuits and a test example of placement.