COMPARATIVE ANALYSIS OF THE BASIC ELEMENT CHARACTERISTICS OF INTEGRATED CIRCUITS BASED ON PLANAR AND THREE-DIMENSIONAL CMOS STRUCTURES

Abstract

At designing complementary metal-oxide semiconductors (CMOS) super-large inte- grated circuits, the most important issue is the selection of the basic elements on the basis of which microelectronic systems are developed. In this paper, a comparative analysis of the basic elements of integrated circuits made on the basis of planar and three-dimensional structures is carried out. In case of designing integrated circuits with processing standards of 100 nm or lower, it is necessary to take into account short-channel effects in transistors caused by a fun- damentally new distribution of the electrical potential in the channel of the transistor. These effects reduce the threshold voltage and increase the leakage currents by four orders of magni- tude when the voltage across the drain varies from 50 mV to 3 V at zero gate voltage. Studies show that in each technological transition, the density of the arrangement of transistors dou- bles, the time delays in signal propagation and the threshold voltage decreases by 30% and 15%, respectively. Therefore, in case of designing super-large integrated circuits, the scaling becomes a problem. One of the possible ways to solve this problem is a fundamentally new approach to their design, consisting in the transition from the planar technology of manufactur- ing transistors to transistors with a three-dimensional shutter structure (FinFET). The peculiari- ties of the structures of FinFET transistors with two or more gates and their manufacturing technology are considered. Increasing the density of the layout of transistors can be achieved by using spacers and choosing the height of the "fin". The basic designs of FinFET transistors are presented and their peculiarities are analyzed. According to the technological standards of 28/32 nm, using the TSMC models and the Tspice modeling tool in the Tanner environment, the simulation of NAND, NOR, XOR, XNOR excluding basic elements based on CMOS pla- nar and FinFET transistors is carried out, the power-delay-product parameter (PDP) is esti- mated based on the simulation results.