TRANSFORMING THE VERILOG DESCRIPTION OF THE LOGICAL CIRCUIT IN THE SIGNAL FLOW GRAPH

Authors

A.G. HARUTYUNYAN National Polytechnic University of Armenia Author
A.R. MARTIROSYAN National Polytechnic University of Armenia Author

Keywords:

signal flow graph, ranking of elements, the binary tree

Abstract

A method for converting the Verilog description of a logical circuit into a signal flow graph is proposed, which makes it possible to automate the placement of elements based on the ranking of a given circuit. The proposed method is based on the presentation of the Verilog description of the logical scheme in the form of a binary data tree. The software of the proposed method is implemented.

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Published

13.04.2026

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