A METHOD TO REDUCE THE DYNAMIC POWER IN THE LOGICAL CHAIN OF CMOS VERY-LARGE-SCALE INTEGRATED CIRCUITS

K.O. PETROSYAN; G.SH. MELIKYAN

A METHOD TO REDUCE THE DYNAMIC POWER IN THE LOGICAL CHAIN OF CMOS VERY-LARGE-SCALE INTEGRATED CIRCUITS

Authors

K.O. PETROSYAN National Polytechnic University of Armenia Author
G.SH. MELIKYAN National Polytechnic University of Armenia Author

Keywords:

modeling, power, channel, delay

Abstract

Methods to reduce the dynamic dissipation power are investigated. A method for reducing the dynamic power VLSI CMOS logic circuits using inverters of different channel lengths is recommended.

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Published

17.07.2026

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Vol. 1 (2016)

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A METHOD TO REDUCE THE DYNAMIC POWER IN THE LOGICAL CHAIN OF CMOS VERY-LARGE-SCALE INTEGRATED CIRCUITS

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