PROCESSING AND HARDWARE IMPLEMENTATION OF DEVICES FORMING INTERNAL REGISTERS OF SUPERSCALAR PROCESSOR

Abstract

The issues of hardware implementation of devices forming Tag the internal registers of a superscalar processor have been studied. Structural processing of the blocks forming Tag the internal registers of superscalar processors is carried out, in particular, the block diagrams of devices that form the general-purpose, control, and status registers, that is, those internal registers whose operation is also organized by hardware. Schemes of the designed devices have been developed, performance and hardware costs in terms of FPGA resources have been assessed.