DESIGN OF RESISTANCE CALIBRATION CIRCUIT OF THE NODES OF I/O BASED ON THE 14 NM TECHNOLOGY CMOS

Abstract

An analog-to-digital system has been developed for matching the resistance of an I/O node that will have a maximum resistance deviation of up to 2% for the 14nm CMOS process. The operating voltage of the circuit is 1.8 V. During the research, one scheme was observed, parametric optimization was performed through the SPICE model, physical modeling was performed using Custom Compiler. The results were displayed and measured using WaveView. Also a behavioral description of the leading/control logic was given and a corresponding scheme was synthesized using the Verilog and DesCompiler tools.