DEVELOPING THE BLOCK OF CORRELATION PREDICTION OF BRANCH INSTRUCTIONS IN MODERN PROCESSORS

Authors

G.A. SHAHBAZYAN National Polytechnic University of Armenia Author

Keywords:

instruction-level parallelism (pipelining), correlation prediction system, branch history register (BHR), pattern history table (PHT)

Abstract

A system, implementing the correlation prediction of branch instructions at pipelined processing in modern processors is considered, and the block diagram of the prediction block is developed. Estimates of the developed block of correlation prediction from the point of view of speed and hardware costs when designing based on FPGA are given.

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Published

01.04.2026

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