DEVELOPMENT OF METHODS FOR CONSTRUCTING HIGH-SPEED DECODERS WITH LOW POWER CONSUMPTION OF RANDOM ACCESS MEMORY

Abstract

The principles of constructing decoders of linear and pyramidal addresses with the mixed logic of static random access memory devices are investigated. Corresponding equations for describing the output signal of decoders are given, as well as formulas for calculating AND-NOT, OR-NOT, and simultaneously constructed logical elements with them, as well as the precise table of the decoders of direct and inverse addresses. It is proposed to create logic elements using shut-off valves and using preliminary converters in descriptor circuits based on optimized logic elements. A new method for designing decoders is proposed, on the basis of which four types of constructions of decoders are developed: with low power consumption, high-speed, inverted and standard. The modeling of the work of the proposed logic elements has been performed by SAED 28 nm software. The electrical circuits of descriptors 2-4 and 4-16 based on complementary metal-oxide-semiconductor structures are considered. The proposed method has performed a comparative analysis of the time of standard logic elements and the time of power consumption and propagation delay of the decoder signal. One of the two schemes of the proposed 4-16 decoders provides approximately 36% low power consumption by reducing the number of transistors, and the other - approximately 6.5% high speed performance. The disadvantage of the proposed decoder scheme is the asymmetry in the circuits due to the difference in input capabilities. In this case, it is necessary to correctly select the connection of the inputs of the logic elements, that is, the signal that will switch faster to the circuit must be connected to the input with a small input ability of the logic element, and the slowly switched signal to the input with a large input ability of the logic element.