COMPARATIVE ANALYSIS OF THE METHODS FOR CONSTRUCTING DECODERS

Abstract

Ways of constructing address decoders - one of the main components of memory devices are investigated. The description system of equations and terms for determining the number of two-input AND gates or NAND and NOR the simultaneous use of these elements for their construction are introduced. Eight and sixteen bit decoders with three engineering solutions: linear, on the logical elements NAND and NOR, and by the proposed methods implemented by the CMOS technology are considered. For the design of address decoders, in order to ensure a minimum of dynamic power dissipation, two ways of creating them to be used for the right combination of logic elements are analized. The simulation of the address decoder with structures 3×8 and 4×16 with three options for constructing them, by using Hspice software tools and physical design, by using software Custome Designer package are carried out. A comparative analysis of timing, power and footprint is performed. Its shows that the proposed method provides a small spread delay times and the fronts of output signals, which decreases with increasing the bit decoder, which is a very important indicator of memory. It is also shown that this method of construction allows the address decoders to create decoders which lack the possibility of false signals resulting in a decrease in dynamic power dissipation.