MODELING THE TIME RESPONSE OF CMOS STATIC RANDOM ACCESS MEMORY
Keywords:
memory element, information capacity, performance, modeling, amplifier, line, reading, recording.Abstract
The time response CMOS of static random access memory (SRAM) with technological standards SAED EDK 28 nm is investigated and modeled. The schemes of the amplifier recording, as well as the bit line and memory charging calculations of the memory wire capacities are introduced. The obtained results allow to select the information capacity and performance of VLSI SRAM.
