CALCULATION OF DECOUPLING THE CAPACITORS’ CAPACITANCE USING THE POWERIC DECAP CALCULATOR SUBSYSTEM
DOI:
https://doi.org/10.53297/18293336-2022.2-81Keywords:
integrated circuits, metal layer, software tool, transistor, capacitance, MOS, MOMAbstract
The design of a software tool for calculating decoupling capacitors in integrated circuits has been proposed, which allows the user to make accurate schematic calculations of the solutions used in those circuits without programming knowledge through simple inputs.
PowerIC Decap Calculator allows the user to calculate the required capacity of decoupling capacitors, allowing it to be placed on the free surface of the integrated circuit (IC) entered by the designer. The capacity calculation is performed taking into account the existing and proposed methods of design of decongesting capacitors, which in turn increases the flexibility of the proposed solution.
The introduction of the PowerIC Decap Calculator in the design process of ICs allows, in the early stages of the design when the physical design of the IC has not been completed, to perform the calculations of decoupling capacitors’ capacities based on the values of the limitations in the current area.
As a result of calculation, in the case of designing decoupling capacitors with the joint use of MOM and capacitors with MOS structures, the area occupied by these elements in IC is reduced by 1.5 times, at the same time, the dependence of these elements on the deviation of technological processes is reduced. The calculation takes about 4 minutes.
