SELECTION OF A READING AMPLIFIER FOR A FERROELECTRIC STORAGE DEVICE AND CHARACTERISTICS MODELING
Keywords:
ferroelectric storage device, architecture, reading, sensitivity, critical hole, modelingAbstract
Ferroelectric memory devices are studied, which are characterized by high speed, low operating voltages and consumption capacity and compatibility with CMOS technology. The existing ferroelectric storage elements are mainly processed based on the 1T-1C and 2T-2C architectures. The analysis of the FeRAM memory circuitry shows that the 1T-1C structure is currently the most common. The 1T-1C architecture has a smaller memory element area, but a voltage reference is required to read the data. When reading information for accurate differentiation of the voltage on the battery bit line in the 1T1C architecture, the input signal of the amplifier is compared with the constant voltage of the support common to all storage elements. The reference voltage is defined as the arithmetic average of the voltages corresponding to the logical high and low levels. The formation of an accurate level of the reference voltage allows to get the maximum signal voltage for the reading amplifier. The sensitivity of the amplifier circuit is defined as the minimum difference between the read signals and the reference signal. An important issue in the design of ferroelectric storage devices is the development of a reading amplifier with high sensitivity, since in the process of scaling, the reading scheme of ferroelectric storage devices becomes one of the main factors limiting the reduction in the size of storage elements, especially in the case of ultra-low operating voltages and due to lost bit currents lines that further reinforce the limitations of the reading circuit. The increase in the information capacity of the storage device leads to the emergence of a large ability of the bit line and leads to a decrease in the critical parameter of the input voltage of the read amplifier. Thus, the development of high-sensitivity reading amplifiers with a small inlet becomes an important task. For 1T1C architecture, a reading amplifier circuit has been studied and its characteristics are modelled.



