TRANSFORMING THE VERILOG DESCRIPTION OF THE LOGICAL CIRCUIT IN THE SIGNAL FLOW GRAPH

Abstract

A method for converting the Verilog description of a logical circuit into a signal flow graph is proposed, which makes it possible to automate the placement of elements based on the ranking of a given circuit. The proposed method is based on the presentation of the Verilog description of the logical scheme in the form of a binary data tree. The software of the proposed method is implemented.